The present invention relates to an integrated circuit architecture for CMOS imagers. More specifically, the present invention relates to methods and apparatus for masking or correcting faults in individual pixels of CMOS imagers.
CMOS image sensors are now becoming competitive with charge coupled device (“CCD”) array image sensors. Potential applications include digital cameras, night time driving displays for automobiles, and computer peripherals for document capture and visual communications.
Since the 1970s, CCD arrays have dominated the electronic image sensor market. They have outperformed CMOS array sensors in most areas, including quantum efficiency, optical fill factor (the fraction of a pixel used for detection), charge transfer efficiency, readout rate, readout noise, and dynamic range. However, the steady improvement in CMOS technology (including increasingly small device size) has moved CMOS image sensors into a competitive posture. Further, in comparison to CCD technology, CMOS technology provides lower power consumption, increased functionality, and potentially lower cost. Researchers now envision single chip CMOS cameras having (a) integrated timing and control electronics, (b) a sensor array, (c) signal processing electronics, (d) an analog-to-digital converter, and (e) interface electronics. See Fossum, “CMOS Image Sensors: Electronic Camera On A Chip,” 1995 IEDM Technical Digest, Wash. DC, Dec. 10-13, 1995, pp. 17-25 which is incorporated herein by reference for all purposes.
CCD arrays are limited in that all image data is read by shifting analog charge packets from the CCD array interior to the periphery in a pixel-by-pixel manner. Unfortunately, the pixels of the CCD array are not randomly addressable. In addition, due to voltage, capacitance, and process constraints, CCD arrays are not well suited to integration at the level possible in CMOS integrated circuits. Hence, any supplemental processing circuitry required for CCD sensors (e.g., memory for storing information related to the sensor) must generally be provided on separate chips. This, of course, increases the system's cost.
A persistent problem of both CMOS and CCD image sensor technologies is image degradation due to faulty pixels. Such faulty pixels arise from processing variations inherent in fabrication of numerous sensor chips. A pixel's fault may be manifested by an output indicative of a radiation exposure that does not accurately reflect the actual radiation exposure to which the pixel was exposed. For example, a pixel that outputs more charge than is expected upon exposure to a particular amount of radiation appears as a bright spot in an image. Similarly, a pixel that outputs less charge than expected appears as a dark spot.
Typically, image sensors are tested after fabrication to identify the number of faulty pixels that they contain. If any sensor has more than a specified number of faulty pixels, it must be rejected. Thus, sensor yield is limited by the number of faulty pixels typically produced on a chip. Not surprisingly, wide area sensors having large numbers of pixels have relatively low yields because they tend to have higher numbers of faulty pixels (the number of faulty pixels per total number of pixels is approximately constant for a given fabrication technology).
While careful screening of image sensors after fabrication can locate defective arrays, it cannot prevent sensors from degrading during normal use. Pixels sometimes develop such faults during normal operation. Unfortunately, no effective mechanism exists for identifying and correcting such faults.
What is needed therefore is an improved image sensor that can mask or otherwise correct defective pixels soon after the sensor is fabricated and during its lifetime.